You are designing a real‑time sensor data acquisition system on an ARM Cortex‑M4 microcontroller. The system must read data from an ADC at 1 kHz, process it, and transmit over UART at 115200 baud. Explain how you would structure the firmware to meet timing constraints and avoid data loss. What scheduling strategy would you use, and how would you handle priority inversion?

Use the CIRCLES framework: Clarify requirements, Identify constraints, Recommend architecture, Choose scheduling, List trade‑offs, Execute plan, Summarize. 1) Clarify: 1 kHz ADC, UART 115200 baud, no data loss. 2) Constraints: ISR latency <1 ms, memory <64 KB, power <50 mW. 3) Architecture: DMA for ADC, double‑buffered FIFO, ISR minimal, RTOS task for processing/transmission. 4) Scheduling: RTOS preemptive with priority inheritance; ADC ISR high priority, processing task medium, UART task low. 5) Trade‑offs: DMA reduces CPU load but requires buffer alignment; RTOS adds overhead but simplifies priority inversion handling. 6) Execute: Configure DMA, set up circular buffers, enable priority inheritance, test jitter. 7) Summarize: This design meets timing, avoids data loss, and handles priority inversion.

I would start by clarifying the functional and non‑functional requirements: 1 kHz ADC sampling, 115200 baud UART transmission, no data loss, and low interrupt latency. Next, I’d identify constraints: ISR latency <1 ms, memory <64 KB, and power <50 mW. The architecture would use DMA for ADC to offload the CPU, a circular double‑buffer FIFO to decouple ISR and processing, and a lightweight RTOS with priority inheritance to handle priority inversion. Scheduling would set the ADC ISR as the highest priority, the data‑processing task as medium, and the UART transmission task as low. I’d implement a watchdog to catch hangs and use memory‑mapped I/O for efficient register access. Finally, I’d validate timing with a real‑time profiler, ensuring jitter stays below 0.5 %. This design meets timing constraints, prevents data loss, and gracefully handles priority inversion.